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32bit single precision floating point addition unit(verilog) by offsetcomp

May 5th, 2012

A verilog code for 32bit single precision floating point addition unit. The detail will be provided. (Budget: $30-$250 USD, Jobs: Software Architecture, Verilog / VHDL)

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VHDL and microcontroller questions needing solutions by adeypeter

April 30th, 2012

I have a set of VHDL and microcontroller questions needing solution. They are basic questions if you know this topic. I have attached the questions for your assesement. Please only bid if you can provide… (Budget: $30-$250 USD, Jobs: Electrical Engineering, Electronics, Microcontroller, Telecommunications Engineering, Verilog / VHDL)

Original post by Freelancer.com - New Projects

 

A Simple State Machine including Test bench by computermech

April 22nd, 2012

A Simple State Machine including Test bench Implement a simple state machine that controls the sequencing of the line LdA, LdB and LdS. The objective is to enable each of these at successive clock cycles… (Budget: $30-$250 AUD, Jobs: Verilog / VHDL)

Original post by Freelancer.com - New Projects

 

SONET Frame by vwase01

April 4th, 2012

>>That is, convert input from serial to parallel, store data in RAM, take data from ram and send to other data lines. >>6-8 input detector-> counter value "4" puts data in to ram, then serial to paralel converter put in ram… (Budget: $30-$250 USD, Jobs: Verilog / VHDL)

Original post by Freelancer.com - New Projects

 

VHDL Recogntiion system by sushma454

March 6th, 2012

Please find the file attached. (Budget: $30-$250 USD, Jobs: Electrical Engineering, Electronics, PCB Layout, Software Architecture, Verilog / VHDL)

Original post by Freelancer.com - New Projects

 

CDFG generator for VERILOG/VHDL by bhanu27

March 4th, 2012

Given a RTL description of a hardware design in verilog or VHDL. I need to build a tool which can generate a CDFG (control data flow graph) and also the ability to graphically view the CDFG (Budget: $750-$1500 USD, Jobs: C Programming, C++ Programming, Python, Verilog / VHDL)

Original post by Freelancer.com - New Projects

 

Design Digital clock using Block Diagram(Altera’s QuartusII) by Manlucky027

March 2nd, 2012

Hello I want a Block Diagram by using Altera’s QuartusII for a digital clock to present hours and minutes with 12-hr format with an AM/PM .The clock must havecontrol input signals for Start, Pause and Reset… (Budget: $30-$250 USD, Jobs: Electrical Engineering, Engineering, Verilog / VHDL)

Original post by Freelancer.com - New Projects

 

Xilinx in-system programming using microcontroller by myil

January 4th, 2012

Attached appnote on xilinx on below details. Programming Xilinx CPLDs,FPGAs, and Configuration PROMs on Xilinx In-System Programming Using an Embedded Microcontroller. experience on Firmware implementaion using embedded microcontroller like ( freescale) or any and to program xilinx FPGA … (Budget: $30-$250 USD, Jobs: Electronics, Microcontroller, Verilog / VHDL)

Original post by Freelancer.com - New Projects

 

Xilinx in-system programming using Embedded microcontroller by myil

January 1st, 2012

Programming Xilinx CPLDs,FPGAs, and Configuration PROMs on Xilinx In-System Programming Using an Embedded Microcontroller. experience on Firmware implementaion using embedded microcontroller like ( freescale) or any and to program xilinx FPGA … (Budget: $250-$750 USD, Jobs: Electronics, Microcontroller, Verilog / VHDL)

Original post by Freelancer.com - New Projects

 

Verilogprojectassap by kazimcan

December 26th, 2011

Mastermind desing with verilog. Details are on the file please read it (Budget: $30-$250 USD, Jobs: Verilog / VHDL)

Original post by Freelancer.com - New Projects

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